1. Field of Invention
The present invention relates to the field of computer processors. More specifically, the invention relates to manipulation of bit fields by computer processors.
2. Description of Related Art
In typical computer systems, processors are utilized in order to perform specific operations on data, the data usually consisting of a large number of bits such as 64 bits, using a set of instructions that produce a desired result. For example, the processor may execute a subtraction instruction, wherein a first 64-bit value is subtracted from a second 64 bit value resulting in a third 64 bit value which can be stored to a memory or utilized for further calculations or instructions. However, with the advance in technology and utilization of multimedia applications, such as enhanced graphic displays, image processing, recognition algorithms and video compression/decompression, modern multimedia applications require the manipulation of large amounts of data which may be represented in a small number of bits. Another application which requires similar bit intensive manipulation is packet switching networks. Packet switching networks, similar to multimedia applications, require the manipulation of large amounts of data which may represented in a small number of bits, these amount of data are typically refered to as network data packets. Typically, each of these applications require one or more algorithms, with each algorithm requiring a number of operations to be executed. For example, an algorithm may require numerous operations, such as load, shift, add, and compare, for completion of the algorithm.
Conventional processors provide instructions for separately manipulating each of the elements in these network data packets. For example, an add instruction adds together "corresponding" data elements from a first network data packet and a second network data packet, in order to complete the add instruction. Therefore, if an application requires detailed and expansive algorithms, like packet switching networks, which contain a series of operations which must be performed on a large number of data elements, it is highly desirable to manipulate the network data packets and perform the operations in parallel utilizing the network data packet instruction. By utilizing the representative data contained within the network data packets, and performing the operations in parallel, the processor can process complex applications most efficiently.
A typical application of the advantages of using network data packets is in relation to an operation called check summing. Check summing is an operation for determining the sum of data values contained within a network data packet. Checksum generation is extremely useful, for example in, communications among processors interconnected in a network. In a typical network, a network data packet containing, for example, a binary-encoded bit string of control information and data, may be transmitted from an originating processor to a destination processor, or through one or more intermediate processors. However, during transmission, errors may be introduced into the network data packet by, for example, interference or spurious network noise, resulting in the processing of an erroneous network data packet. The processing of such an erroneous network data packet by the processor may result in the processor rejecting the network data packet, or even causing the processor itself to fail.
To guard against such rejections and failures in relation to network data packets, an error-checking mechanism may be employed in order to verify that the bits contained in the received data is the same as, or correct in comparison, to the transmitted data. The error-checking mechanism allows for erroneous network data packets to be discarded prior to processing, while allowing correct network data packets to pass to the targeted processor. Typically, the checking mechanism comprises generating an arithmetic quantity based upon some, or all, of the bits which are to be transmitted from the originating processor, including the arithmetic quantity in the network data packet when the network data packet is actually transmitted, and then verifying the arithmetic quantity when the network data packet is received by an intermediate or destination processor.
In order to accomplish the traditional generation of checksum values of network data packets, bit fields located within the network data packet's binary-encoded bit string of control information and data must be manipulated in order to obtain the necessary arithmetic quantity. Primarily, checksum generation is accomplished through lane addition, wherein an add instruction adds together "corresponding" or "aligned" data elements or bit fields from a first network data packet and a second network data packet, in order to generate a checksum value which corresponds to a specified transmitted network data packet value.
However, the ability to manipulate such data elements or bit fields in a general purpose computer (GPC) ranges over a wide area, as GPC's are often adapted to the job of packet processing or switching through the introduction of specialized memory subsystems and I/O devices. Some GPC's have no direct support for manipulation of bit fields, but instead rely on "shift", "and", and "or" instructions in order to effect bit field manipulation. While other GPC's provide field insert and extract instructions for general registers, and further, other GPC's provide field insert and extract instructions for memory locations. However, GPC designs all take the same approach to bit field manipulation: isolation of the bit field, manipulation of the bit field, and reintegration of the bit field into a larger convenient data item for processing. Since, the typical GPC requires the individual steps of isolation, manipulation, and reintegration, the GPC processor speed and efficiency is greatly reduced, as the processor must execute each individual operation in order to perform the required steps before the entire instruction is completed.
Moreover, the typical GPC architect has control of both the GPC's processor and compiler and therefore the layout of data structures in memory. This allows the programmer and compiler to `align` data items conveniently and even change the size of the data item at will. Some GPC architects have gone so far as to only support a single size of data items, thereby requiring the compiler to generate extra instructions when an inconvenient data size is needed for space reasons. Similarly, due to the fact that the extra instructions require certain operations to be executed before processing the packet, the GPC processor speed and efficiency is further reduced.
The format of data for network data packet processing, on the other hand, is not under the control of a designer or compiler writer, rather it is controlled by standards committees. Further, these committees are generally more concerned with minimizing the size of the network data packet, in order to provide fast throughput and increase processing speed, than with ease of processing. Consequently, network data packet formats often include unusual data sizes, such as 3-bit or 5-bit numbers, therefore the packet processor designer must consider the direct manipulation of these unusual data sizes in order to provide a network data packet processor that can quickly and easily manipulate unusual size data items. Since network data packet processing is input/output (I/O) intensive, the goal in network data packet processing is to receive a network data packet from an I/O channel, process (switch) the network data packet, and transmit the network data packet out another channel in minimal time.